1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, more particularly to a semiconductor integrated circuit device comprising a redundancy constitution.
2. Description of the Related Art
A semiconductor integrated circuit device having a redundancy circuit to relieve defective circuit portions in a memory and the like requires a primary checking for examining whether defects can be relieved by the use of a redundancy circuit, during a selection step performed for the integrated circuit on a wafer. The semiconductor integrated circuit device requires also a secondary checking for examining whether products, after having been relieved by the use of the redundancy circuit, are non-defectives, during that selection step. In the primary checking, a plurality of checkings are performed, in which judgments are made to sort the products into non-defectives, redundancy products which are used as non-defectives by use of a redundancy circuit, and defectives which have no possibility of being used as non-defectives in spite of the use of a redundancy circuit. After the primary checking, the redundancy products are relieved under the condition that a redundancy circuit is used for them. Thereafter, in the secondary checking, in order to examine whether the redundancy products are non-defectives, all of the same checking items as those in the primary checking are examined. However, since the secondary checking is conducted for the semiconductor integrated circuit device on the wafer, the same tests are conducted for the products regarded as defectives in the primary checking. The defectives in the primary checking are always regarded as the defectives, so that examining the foregoing products in the secondary checking prolongs the time per wafer for performing the secondary checking. In order to shorten the time for the secondary checking, the following two ways have been used.
First, in a first conventional testing method of a semiconductor integrated circuit device disclosed in Japanese Patent Application Laid Open No. 183832/1989, it is decided whether a redundancy circuit can be substituted for the defective circuit, and the semiconductor integrated circuit device subjected to the checking is destroyed if the substitution for the defective circuit by the redundancy circuit is impossible.
The first conventional testing method of a semiconductor integrated circuit device will be described with reference to the FIG. 1. flow chart. After a primary checking is executed (Step P1), if a chip can be relieved by use of a redundancy circuit, a relieving action is performed. A chip which is regarded as a defective in a primary checking, even though a redundancy circuit is used, is destroyed using a high voltage or laser light beam at the time as the action to relieve a redundancy product (Step P3). At the beginning of the secondary checking, the defectives of the primary checking can be discriminated by a contact check without executing all of the same checking items as those of the primary checking (Step P4). If the contact check is passed, an operation test is executed (Step P5). Thus, it will be possible to shorten the time of the secondary checking.
Next, in a second conventional method of testing a semiconductor integrated circuit device, disclosed in Japanese Patent Application Laid Open No. 282892/1993, non-defectives are programmed in a primary checking, whereby a circuit is set so that a chip is discriminated as a non-defective in an examination at an early stage of a secondary checking. Therefore, the chip decided as the non-defective is not subjected to the secondary checking and unnecessary examinations in the secondary checking can be omitted.
The second conventional method of testing a semiconductor integrated circuit device will be described with reference to the FIG. 2 flow chart. After a primary checking is executed (Step Q1), discrimination data relating to non-defectives and defectives in the primary checking are stored using a programming circuit installed in the device (Step Q2). At the time of the secondary checking if the contact check is passed (Step Q3), the discrimination data relating to the non-defective and the defective status are read out (Step Q4). If the product is regarded as a defective as a result of the primary checking, the product is treated as defective, and the examination of this product is not performed so that the checking time is shortened.
If the product is regarded as non-defective as a result of the primary checking, an operation test is executed (Step Q5).
Next, referring to FIG. 3 showing the programming circuit, the programming circuit 101 is connected with an input terminal T1 used for testing and an output terminal T2, via a NAND circuit A101. The result of a logic product of an output level of the programming circuit 101 and an input level of the input terminal T1 for testing is output from the NAND circuit A101 to the output terminal T2 for testing.
When a fuse F101 of the program circuit 101 is not cut, a signal P at the connection node of the fuse F101 and a resistor R101 is high in level. This high level of the signal P is inverted by an inverter I101 and an output signal Q from the inverter I101 is low in level. Therefore, since this one of the inputs to the NAND circuit A101 is always low in level, a voltage level of the output terminal T2 for testing is always high in level whether or not a level of a voltage applied to the input terminal T1 for testing is high in level or low in level. When the fuse F101 of the program circuit 101 is cut, the signal P is set to be low in level, this low level of the signal P is inverted by the inverter I101 so that the signal Q is set to be high in level. As a result, since one of the inputs to the NAND circuit A101 is always high in level, upon application of a high level to the input terminal T1 for testing, a low level is output to the output terminal T2 for testing. According to the foregoing procedures, a state of the program circuit can be detected.
Since, in the foregoing testing method of conventional first semiconductor integrated circuit device, the chip regarded as defective in the primary checking is destroyed at the time of the relieving action for the redundancy product, it is impossible to specify which portion is defective. Therefore, there has been a drawback that after the secondary checking an execution of analyzing for the products decided as the defectives by the primary checking is difficult.
Moreover, since in the foregoing method of testing conventional second semiconductor integrated circuit devices, it is necessary to perform examinations for all of the chips on the wafer in the secondary checking, the examinations being for checking the data of results of the primary checking and being originally unnecessary in the second checking, and the time for the secondary checking is more prolonged than in the conventional first semiconductor integrated circuit device. Particularly, the checking time is prolonged when the defectives in the primary checking are not present on the wafer. An example will be made using numerical values concretely. It is assumed that 500 chips are present on the wafer and 1 second is needed to examine data relating to the result of checking the quality of the products on one chip. When the defectives of the primary checking are not present in 500 chips, the checking time per one wafer is prolonged by 500 seconds.